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NCP5210 3-in-1 PWM Dual Buck and Linear DDR Power Controller
The NCP5210, 3-in-1 PWM Dual Buck and Linear DDR Power Controller, is a complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage. This IC contains two synchronous PWM buck controller for driving four external N-Ch FETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. The DDR memory termination regulator (VTT) is designed to track at the half of the reference voltage with sourcing and sinking current. Protective features include, soft-start circuitry, undervoltage monitoring of 5VDUAL and BOOT voltage, and thermal shutdown. The device is housed in a thermal enhanced space-saving QFN-20 package.
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20
1 NCP5210 AWLYYWW
1
QFN-20 MN SUFFIX CASE 505AB
* Incorporates Synchronous PWM Buck Controllers for VDDQ and * * * * * * * * * * * * * *
VMCH Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A All External Power MOSFETs are N-Channel Adjustable VDDQ and VMCH by External Dividers VTT Tracks at Half the Reference Voltage Fixed Switching Frequency of 250 kHz for VDDQ and VMCH Doubled Switching Frequency of 500 kHz for VDDQ Controller in Standby Mode to Optimize Inductor Current Ripple and Efficiency Soft-Start Protection for all Controllers Undervoltage Monitor of Supply Voltages Overcurrent Protections for DDQ and VTT Regulators Fully Complies with ACPI Power Sequencing Specifications Short Circuit Protection Prevents Damage to Power Supply Due to Reverse DIMM Insertion Thermal Shutdown 5x6 QFN-20 Package Pb-Free Package is Available*
NCP5210 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
PIN CONNECTIONS
COMP FBDDQ SS PGND VTT VDDQ AGND FBVTT DDQ_REF FB1P5 SW_DDQ BG_DDQ TG_DDQ BOOT 5VDUAL COMP_1P5 BUF_Cut TG_1P5 BG_1P5 GND_1P5
NOTE: Pin 21 is the thermal pad on the bottom of the device.
Applications
ORDERING INFORMATION
Device NCP5210MNR2 NCP5210MNR2G Package QFN-20 QFN-20 (Pb-Free) Shipping 2500 Tape & Reel 2500 Tape & Reel
* DDR I and DDR II Memory and MCH Power Supply
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2005
1
January, 2005 - Rev. 4
Publication Order Number: NCP5210/D
NCP5210
BUF_Cut BUF_Cut SS 12 V CSS BOOT 1.25 V, 2 Apk COUT2 FBVTT VTT VTT 5VDUAL 13 V Zener 5VDUAL
AGND DDQ_REF VDDQ CZM2 R5 RZM2 CZM1 CPM1 RZM1 5VDUAL R6 M3 VMCH L FBDDQ TG_1P5 COMP_1P5 BG_DDQ FB_1P5 PGND COMP CZ1 RZ1 TG_DDQ
M1 VDDQ L 2.5 V, 20 A COUT1 M2
NCP5210
SW_DDQ
CZ2 R1
CP1
RZ2
R2 1.5 V, 10 A COUT3 M4 BG_1P5 VDDQ GND_1P5
Figure 1. Application Diagram
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NCP5210
VREF VOLTAGE and CURRENT REFERENCE BUF_CUT VCC R10 VREF R11 VOCP + VCC BOOT_ UVLO _BOOTGD CONTROL LOGIC S0 S3
VCC THERMAL SHUTDOWN
12 V BOOT
_VREFGD TSD
13 V Zener
5VDUAL 5VDUAL
5VDUAL
R12 R13 VREF
UVLO _5VDLGD
VDDQ and V1P5 PWM LOGIC PGND VCC BG_DDQ PGND PGND TG_DDQ SW_DDQ
CSS
OSC
S0 S3 AMP A1 VCC VREF
1805 Phase Shift
5VDUAL S0 R16 VTT Regulation Control R17 R18 R19 AGND 5VDUAL M3 M2 VTT VTT COUT2 VDDQ
AGND
AGND
Figure 2. Internal Block Diagram
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- VCC PGND
5VDUAL_
+
5VDUAL
ILIM
M1 L VDDQ
COUT1 M2
COMP CZ1 RZ1 FBDDQ
CZ2 CP1 RZ2 5VDUAL M3
R1
R2 VMCH
TP_1P5 PGND BG_1P5 GND_1P5 PGND AMP_MCH VREF A1 CZM1 RZM1 FBDDQ COMP_1P5 CZM2 CPM1 RZM2 M4
L2
COUT2
RM1
RM2
DDQ_REF
PGND
FBVTT
NCP5210
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Symbol COMP FBDDQ SS PGND VTT VDDQ AGND FBVTT DDQ_REF FB1P5 GND_1P5 BG_1P5 TG_1P5 BUF_Cut COMP_1P5 5VDUAL BOOT TG_DDQ BG_DDQ SW_DDQ TH_PAD VDDQ error amplifier compensation node. DDQ regulator feedback pin. Soft-start pin of DDQ and MCH. Power ground. VTT regulator output. Power input for VTT linear regulator. Analog ground connection and remote ground sense. VTT regulator pin for closed loop regulation. Reference voltage input of VTT regulator. V1P5 switching regulator feedback pin. Power ground for V1P5 regulator. Gate driver output for V1P5 regulator low side N-Channel Power FET. Gate driver output for V1P5 regulator high side N-Channel Power FET. Active HIGH control signal to activate S3 sleep state. V1P5 error amplifier compensation node. 5.0 V Dual supply input, which is monitored by undervoltage lock out circuitry. Gate driver input supply, which is monitored by undervoltage lock out circuitry, and a boost capacitor connection between SWDDQ and this pin. Gate driver output for DDQ regulator high side N-Channel Power FET. Gate driver output for DDQ regulator low side N-Channel Power FET. DDQ regulator switch node and current limit sense input. Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC. Description
MAXIMUM RATINGS
Rating Power Supply Voltage (Pin 16) to AGND (Pin 7) BOOT (Pin 17) to AGND (Pin 7) Gate Drive (Pins 12, 13, 18, 19) to AGND (Pin 7) Input / Output Pins to AGND (Pin 7) Pins 1-3, 5-6, 8-10, 14-15, 20 PGND (Pin 4), GND_1P5 (Pin 11) to AGND (Pin 7) Thermal Characteristics, QFN-20 Plastic Package Thermal Resistance Junction-to-Air Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol 5VDUAL BOOT Vg Value -0.3, 6.0 -0.3, 14 -0.3 DC, -4.0 for t100 ns; 14 -0.3, 6.0 -0.3, 0.3 35 0 to + 150 0 to + 70 - 55 to +150 2.0 Unit V V V
VIO VGND RqJA TJ TA Tstg MSL
V V C/W C C C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) "200 V per JEDEC standard: JESD22-A115. 2. Latchup Current Maximum Rating: "150 mA per JEDEC standard: JESD78.
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NCP5210
ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0C to 70C, L = 1.7 mH,
COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF, R1 = 2.166 kW, R2 = 2 kW, RZ1 = 20 kW, RZ2 = 8 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 kW, RM2 = 2 kW, RZM1 = 20 kW, RZM2 = 8 W, CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nF for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ. Characteristic Symbol Test Conditions Min Typ Max Unit
SUPPLY VOLTAGE 5VDUAL Operating Voltage BOOT Operating Voltage SUPPLY CURRENT S0 Mode Supply Current from 5VDUAL S3 Mode Supply Current from 5VDUAL S5 Mode Supply Current from 5VDUAL S0 Mode Supply Current from BOOT S3 Mode Supply Current from BOOT UNDER-VOLTAGE-MONITOR 5VDUAL UVLO Upper Threshold 5VDUAL UVLO Hysteresis BOOT UVLO Upper Threshold BOOT UVLO Hysteresis THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis DDQ SWITCHING REGULATOR FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency in S0 Mode Oscillator Frequency in S3 Mode Oscillator Ramp Amplitude Current Limit Blanking Time in S0 Mode Current Limit Threshold Offset from 5VDUAL Minimum Duty Cycle Maximum Duty Cycle Soft-Start Pin Current for DDQ DDQ ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate 3. Guaranteed by design, not tested in production. GAINDDQ GBWDDQ SRDDQ (Note 3) COMP PIN to GND = 220 nF, 1.0 W in Series (Note 3) COMP PIN TO GND = 10 pF 70 12 8.0 dB MHz V/mS VFBQ IDDQFB FDDQS0 FDDQS3 dVOSC TDDQbk VOCP Dmin Dmax Iss1 V(SS) = 0 V 4.0 (Note 3) (Note 3) (Note 3) 400 0.8 0 100 TA = 25C TA = 0C to 70C V(FBDDQ) = 1.3 V 217 434 250 500 1.3 1.178 1.166 1.190 1.202 1.214 1.0 283 566 V mA KHz KHz Vp-p nS V % % mA Tsd Tsdhys (Note 3) (Note 3) 145 25 C C V5VDLUV+ V5VDLhys VBOOTUV+ VBOOThys 1.0 250 400 4.4 550 10.4 V mV V V I5VDL_S0 I5VDL_S3 I5VDL_S5 IBOOT_S0 IBOOT_S3 BUF_Cut = LOW, BOOT = 12 V, TG_1P5 and BG_1P5 Open BUF_Cut = HIGH, TG_1P5 and BG_1P5 Open BUF_Cut = LOW, TG_1P5 and BG_1P5 Open BUF_Cut = LOW, BOOT = 12 V, TG_1P5 and BG_1P5 Open BUF_Cut = HIGH, TG_1P5 and BG_1P5 Open 10 5.0 1.0 20 20 mA mA mA mA mA V5VDUAL VBOOT 4.5 5.0 12.0 5.5 13.2 V V
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NCP5210
ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0C to 70C, L = 1.7 mH,
COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF, R1 = 2.166 kW, R2 = 2 kW, RZ1 = 20 kW, RZ2 = 8 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 kW, RM2 = 2 kW, RZM1 = 20 kW, RZM2 = 8 W, CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nF for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ. Characteristic Symbol Test Conditions Min Typ Max Unit
VTT ACTIVE TERMINATION REGULATOR VTT tracking DDQ_REF/2 at S0 mode VTT Source Current Limit VTT Sink Current Limit DDQ_REF Input Resistance CONTROL SECTION BUF_Cut Input Logic HIGH BUF_Cut Input Logic LOW BUF_Cut Input Current GATE DRIVERS TGDDQ Gate Pull-HIGH Resistance TGDDQ Gate Pull-LOW Resistance BGDDQ Gate Pull-HIGH Resistance BGDDQ Gate Pull-LOW Resistance TG1P5 Gate Pull-HIGH Resistance TG1P5 Gate Pull-LOW Resistance BG1P5 Gate Pull-HIGH Resistance BG1P5 Gate Pull-LOW Resistance MCH SWITCHING REGULATOR VFB1P5 Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency Oscillator Ramp Amplitude Minimum Duty Cycle Maximum Duty Cycle Soft-Start Pin Current for V1P5 regulator 4. Guaranteed by design, not tested in production. VFB1P5 I1P5FB F1P5 dV1P5OSC Dmin_1P5 Dmax_1P5 ISS2 (Note 4) 8.0 (Note 4) 0 100 217 250 1.3 TA = 0C to 70C 0.784 0.8 0.816 1.0 283 V mA KHz Vp-p % % mA RH_TG RL_TG RH_BG RL_BG RH_TPG RL_TPG RH_BPG RL_BPG VCC = 12 V, V(TGDDQ) = 11.9 V VCC = 12 V, V(TGDDQ) = 0.1 V VCC = 12 V, V(BGDDQ) = 11.9 V VCC = 12 V, V(BGDDQ) = 0.1 V VCC = 12 V, V(TG1P5) = 11.9 V VCC = 12 V, V(TG1P5) = 0.1 V VCC = 12 V, V(BG1P5) = 11.9 V VCC = 12 V, V(BG1P5) = 0.1 V 3.0 2.5 3.0 1.3 3.0 2.5 3.0 1.3 W W W W W W W W Logic_H Logic_L Ilogic 2.0 0.8 1.0 V V mA dVTTS0 ILIMVTsrc ILIMVTsnk DDQREF IOUT= 0 to 2.0 A (Sink Current) IOUT= 0 to -2.0 A (Source Current) -30 2.0 2.0 50 30 mV A A kW
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NCP5210
TYPICAL OPERATING CHARACTERISTICS
1.196 VFBQ, FEEDBACK VOLTAGE (V) 1.194 1.192 1.19 1.188 1.186 1.184 1.182 SWITCHING FREQUENCY (kHz) 550 S3 MODE 500 450 400 350 300 S0 MODE 250 200 0 20 40 60 TA, AMBIENT TEMPERATURE (C) 80
0
20 40 60 TA, AMBIENT TEMPERATURE (C)
80
Figure 3. VFBQ Feedback Voltage vs. Ambient Temperature
0.81 VFB1P5, FEEDBACK VOLTAGE (V) DVTT, SINK CURRENT LOAD REGULATION (mVp-p) 30 29.5 29 28.5 28 27.5 27 0 20 40 60 TA, AMBIENT TEMPERATURE (C) 80 0
Figure 4. Oscillation Frequency in S0/S3 vs. Ambient Temperature
0.805
0.8
0.795
0.79
2 A Sinking Current with 10 ms Period and 1 ms Pulse Width 20 40 60 TA, AMBIENT TEMPERATURE (C) 80
0.785
Figure 5. VFB1P5 Feedback Voltage vs. Ambient Temperature
DVTT, SOURCE CURRENT LOAD REGULATION (mVp-p) 2 A Sourcing Current with 10 ms Period and 1 ms Pulse Width DVTT, OUTPUT VOLTAGE (VDDQ/2 V) -5 -5.5 -6
Figure 6. VTT Sink Current Load Regulation vs. Ambient Temperature
0.02 0.015 0.01 0.005 0
TA = 25C Sourcing/Sinking Current with 10 ms Period and 1 ms Pulse Width
-6.5 -7
-0.005 -0.01
-7.5 -8
-0.015 -0.02
-0.025 -0.03 -2.5
-1.5 -0.5 0.5 1.5 2.5
-8.5 0
20
40
60
80
TA, AMBIENT TEMPERATURE (C)
IVTT, OUTPUT LOAD CURRENT (A)
Figure 7. VTT Source Current Load Regulation vs. Ambient Temperature
Figure 8. VTT Output Voltage vs. Load Current
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NCP5210
TYPICAL OPERATING WAVEFORMS
Channel 2: VDDQ Output Voltage, 1.0 V/div Channel 3: VTT Output Voltage, 1.0 V/div Channel 4: V1P5 Output Voltage, 1.0 V/div Time Base: 5.0 ms/div
Channel 1: BUF_CUT Pin Voltage, 5.0 V/div Channel 2: VDDQ Output Voltage, AC-Coupled, 20 mV/div Channel 3: VTT Output Voltage, AC-Coupled, 100 mV/div Channel 4: V1P5 Output Voltage, AC-Coupled, 50 mV/div Time Base: 10 ms/div
Figure 9. Power-Up Sequence
Figure 10. S0-S3-S0 Transition
Channel 1: Current Sourced out of VTT, 2.0 A/div Channel 2: VDDQ Output Voltage, AC-Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC-Coupled, 50 mV/div Channel 4: V1P5 Output Voltage, AC-Coupled, 100 mV/div Time Base: 200 ms/div
Channel 1: Current Sunk into of VTT, 2.0 A/div Channel 2: VDDQ Output Voltage, AC-Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC-Coupled, 50 mV/div Channel 4: V1P5 Output Voltage, AC-Coupled, 100 mV/div Time Base: 200 ms/div
Figure 11. VTT Source Current Transient, 0A-2A-0A
Figure 12. VTT Sink Current Transient, 0A-2A-0A
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NCP5210
TYPICAL OPERATING WAVEFORMS
Channel 1: Current Sourced into of VDDQ, 10 A/div Channel 2: VDDQ Output Voltage, AC-Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC-Coupled, 100 mV/div Channel 4: V1P5 Output Voltage, AC-Coupled, 100 mV/div Time Base: 1.0 ms/div
Channel 1: Current Sourced into of V1P5, 10 A/div Channel 2: VDDQ Output Voltage, AC-Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC-Coupled, 50 mV/div Channel 4: V1P5 Output Voltage, AC-Coupled, 100 mV/div Time Base: 1.0 ms/div
Figure 13. VDDQ Source Current Transient, 0A-20A-0A
Figure 14. V1P5 Source Current Transient, 0A-12A-0A
Channel 1: Current Sourced into of VDDQ, 2.0 A/div Channel 2: VDDQ Output Voltage, AC-Coupled, 20 mV/div Time Base: 1.0 ms/div
Figure 15. S3 Mode without 12VATX, 0A-2A-0A
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NCP5210
DETAILED OPERATION DESCRIPTIONS
General S5-To-S0 Mode Power-Up Sequence
The NCP5210 3-In-1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two-quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external N-Ch FETs. The VTT termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at 1/2 VDDQ. The MCH core voltage is created by the secondary switching controller. The inclusion of soft-start, supply undervoltage monitors, short circuit protection and thermal shutdown, makes this device a total power solution for the MCH and DDR memory system. This device is housed in a thermal enhanced space-saving QFN-20 package.
ACPI Control Logic
The ACPI control logic is enabled by the assertion of _VREFGD. Once the ACPI control is activated, the powerup sequence starts by waking up the 5VDUAL voltage monitor block. If the 5VDUAL supply is within the preset levels, the BOOT under voltage monitor block is then enabled. After 12VATX is ready and the BOOT UVLO is asserted LOW, the ACPI control triggers this device from S5 shutdown mode into S0 normal operating mode by activating the soft-start of DDQ switching regulator, providing BUF_CUT remaining LOW. Once the DDQ regulator is in regulation and the soft-start interval is completed, the _INREGDDQ signal is asserted HIGH to enable the VTT regulator as well as the V1P5 switching regulator.
DDQ Switching Regulator
The ACPI control logic is powered by the 5VDUAL supply. External control is applied to the high impedance CMOS input labeled BUF_CUT. This signal and two internal under voltage detectors are used to determine the operating mode according to the state diagram in Figure 17. These UVLOs monitor the external supplies, 5VDUAL and 12VATX, through 5VDUAL and BOOT pins respectively. Two control signals, _5VDUALGD and _BOOTGD, are asserted when the supply voltages are good. The device is powered up initially in the S5 shutdown mode to minimize the power consumption. When all three supply voltages are good and BUF_CUT is LOW, the device enters the S0 normal operating mode. Transition of BUF_CUT from LOW to HIGH in S0 mode triggers the device into S3 sleep mode. In S3 mode 12VATX supply collapses. When BUF_CUT is deasserted the state will change back to S0 mode. The IC can re-enter S5 mode by removing one of the supplies during S0 mode. It should be noted that transitions from S3 to S5 or vice versa are not allowed. A timing diagram is shown in Figure 16. Table 1 summarizes the operating states of all the regulators, as well as the conditions of output pins.
Internal Bandgap Voltage Reference
In S0 mode the DDQ regulator is a switching synchronous rectification buck controller driving two external power N-Ch FETs to supply up to 20 A. It employs voltage mode fixed frequency PWM control with external compensation switching at 250kHz 13.2%. As shown in Figure 2, the VDDQ output voltage is divided down and fed back to the inverting input of an internal amplifier through the FBDDQ pin to close the loop at VDDQ = VFBQ x (1 + R1/R2). This amplifier compares the feedback voltage with an internal reference voltage of 1.190 V to generate an error signal for the PWM comparator. This error signal is compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse-width-modulated signal. The PWM signal drives the external N-Ch FETs via the TG_DDQ and BG_DDQ pins. External inductor L and capacitor COUT1 filter the output waveform. When the IC leaves the S5 state, the VDDQ output voltage ramps up at a soft-start rate controlled by the capacitor at the SS pin. When the regulation of VDDQ is detected in S0 mode, _INREGDDQ goes HIGH to notify the control block. In S3 standby mode, the switching frequency is doubled to reduce the conduction loss in the external N-Ch FETs.
An internal bandgap reference is generated whenever 5VDUAL exceeds 2.7 V. Once this bandgap reference is in regulation, an internal signal _VREFGD is asserted.
Table 1. Mode, Operation and Output Pin Condition
OPERATING CONDITIONS MODE S0 S3 S5 DDQ Normal Standby OFF VTT Normal H-Z H-Z MCH Normal OFF OFF TGDDQ Normal Standby Low OUTPUT PIN CONDITIONS BGDDQ Normal Standby Low TP_1P5 Normal Low Low BG_1P5 Normal Low Low
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NCP5210
For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non-overlap timing control of the complementary gate drive output signals is provided to reduce shoot-through current that degrades efficiency.
Tolerance of VDDQ
at the half of DDQ_REF. This regulator is stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 1-mW to 400 mW.
Fault Protection of VTT Active Terminator
Both the tolerance of VFBQ and the ratio of the external resistor divider R1/R2 impact the precision of VDDQ. With the control loop in regulation, VDDQ = VFBQ x (1 + R1/R2). With a worst case (for all valid operating conditions) VFBQ tolerance of 1.5%, a worst case range of 2% for VDDQ will be assured if the ratio R1/R2 is specified as 1.100 1%.
Fault Protection of VDDQ Regulator
To provide protection for the internal FETs, bi-directional current limit preset at 2.4 A magnitude is implemented. The VTT current limit provides a soft-start function during startup.
MCH Switching Regulator
The secondary switching regulator is identical to the DDQ regulator except the output is 10 A, no fault protection is implemented and the soft-start timing is twice as fast with respect to CSS.
BOOT Pin Supply Voltage
In S0 mode, an internal voltage (VOCP) = 5VDUAL - 0.8 sets the current limit for the high-side switch. The voltage VOCP pin is compared to the voltage at SWDDQ pin when the high-side gate drive is turned on after a fixed period of blanking time to avoid false current limit triggering. When the voltage at SWDDQ is lower than VOCP, an overcurrent condition occurs and all regulators are latched off to protect against overcurrent. The IC can be powered up again if one of the supply voltages, 5VDUAL or 12VATX, is recycled. The main purpose is for fault protection but not to be for an precise current limit. In S3 mode, this overcurrent protection feature is disabled.
Feedback Compensation of VDDQ Regulator
In typical application, a flying capacitor is connected between SWDDQ and BOOT pins. In S0 mode, 12VATX is tied to BOOT pin through a Schottky diode as well. A 13-V Zener clamp circuit must clamp this boot strapping voltage produced by the flying capacitor in S0 mode. In S3 mode the 12VATX is collapsed and the BOOT voltage is created by the Schottky diode between 5VDUAL and BOOT pins as well as the flying capacitor. The BOOT_UVLO works specially. The _BOOTGD goes low and the IC remains in S3 mode.
Thermal Consideration
The compensation network is shown in Figure 2.
VTT Active Terminator
The VTT active terminator is a 2 quadrant linear regulator with two internal N-Ch FETs to provide current sink and source capability up to 2.0 A. It is activated only when the DDQ regulator is in regulation in S0 mode. It draws power from VDDQ with the internal gate drive power derived from 5VDUAL. While VTT output is connecting to the FBVTT pin directly, VTT voltage is designed to automatically track
Assuming an ambient temperature of 50C, the maximum allowed dissipated power of QFN-20 is 2.8 W, which is enough to handle the internal power dissipation in S0 mode. To take full advantage of the thermal capability of this package, the exposed pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact.
Thermal Shutdown
When the chip junction temperature exceeds 145C, the entire IC is shutdown, until the junction temperature drops below 120C. Below which, the chip resumes normal operation.
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NCP5210
5VSTBY or 5VDUAL 12 V 5V BUF_CUT SS pin DDQ-S0 Switching Frequency Doubles
VTT MCH
State
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15 16
17
S0
S3
S0
S5
2. 5VSTBY or 5VSTB is the Ultimate Chip Enable. This supply has to be up first to ensure gates are in known state. 3. 12 V and 5 V supplies can ramp in either order. 4. DDQ will ramp with the tracking of SS pin, timing is 1.2 * CSS / 4 m (sec). 5. DDQ SS is completed, then SS pin is released from DDQ. SS pin is shorted to ground. 5. MCH ramps with the tracking of SS pin ramp, timing is 0.8 * CSS / 8 m (sec). VTT rises. 6. MCH SS is completed, then SS pin is released from MCH. SS pin is shorted to ground. S0 Mode. 7. S3 MODE - BUF_CUT = H. 8. VTT and MCH will be turned off. 9. 12 V and 5 V ramps to 0 V. 10. Standard S3 Mode. 11. 12 V and 5 V ramp back to regulation. 12. BUF_CUT goes LOW. 13. 12 V UVLO = L and BUF_CUT = L. MCH ramps with SS pin, timing is 0.8 * CSS / 8 m (sec). VTT rises. 14. S0 Mode. 15. Prepare S5 Mode - BUF_CUT = L, and 12VUVLO = H or 5VUVLO = H. 16. DDQ, VTT, and MCH Turned OFF. 17. S5 Mode.
Figure 16. NCP5210 Timing Diagram
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NCP5210
S5
BUF_CUT = 0 AND _BOOTGD = 1
BUF_CUT = 0 AND (_BOOTGD = 0)
S0
BUF_CUT = 0 AND _BOOTGD = 1
BUF_CUT = 1
NOTE: All possible state transitions are shown. All unspecified inputs do not cause any state change.
S3
Figure 17. State Transitions Diagram of NCP5210
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12VATX 5VDUAL TP2 5VDUAL +C2 3300 mF C23 10 mF 20 19 18 17 16 5VDUAL 15 COMP_1P5 R4 1 1k DPAK 1 3 +C21 100 mF 4 R9 +C24 470 mF R18 51 k R10 4.7 COMP_1P5 4.7 DPAK 1 3 Q4 40N03R C22 10 mF +C3 3300 mF L3 1.8 mH Q5 C16 40N03R 10 nF 4 Q2 85N02R Filtered 5VDUAL C6 4.7 mF AGND to PGND +C7 2200 mF +C25 2200 mF 2.5 VDDQ R2 2.2 DPAK 1 R3 3 L1 1 mH Filtered 5VDUAL D1 BAT54HT1 D2 BAT54HT1 TP2
R6 8
C9 100 nF R5 2.2 k
C8 10 nF C10 R7 6.8 nF 20 k 1 Vref = 1.20 V 2 3 4 5 VDDQ SGND 6 7 COMP FBDDQ SS PGND VTT VDDQ AGND U1 NCP5210 SW_DDQ BG_DDQ TG_DDQ BOOT 5VDUAL COMP_1P5
VDDQ
4 Q1 85N02R C4 22 nF L2 1.8 mH
ZENER MMSZ13T1 VDDQ
C5 470 mF TP5
R8 2k
C1 33 nF
SGND
SGND 8 FBVTT VDDQ 9 DDQREF C20 10 470 mF FB1P5
14 BUF_CUT BUF_CUT 13 TG_1P5 12 BG_1P5 11 GND_1P5 C11 220 nF
R15 1k
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NCP5210
TP7 1.25 VTT
VTT C12 4.7 mF
14
R16 1k
+C13 470 mF
VMCH R11 2.2 k
TP8 TP6 1.5 VMCH
4 DPAK 1 3
C17 6.8 nF
R12 20 K
C18 R13 100 nF 8
C14 4.7 mF
+C26 2200 mF
+C15 2200 mF R17 1k TP16
Vref = 800 mV SGND AGND to PGND SGND
R14 2k
GND
Figure 18. NCP5210 Typical Application Circuit
NCP5210
Application Circuit Power MOSFET Selection
Figure 18 shows the typical application circuit for NCP5210. The NCP5210 is specifically designed as a total power solution for the MCH and DDR memory system. This diagram contains NCP5210 for driving four external N-Ch FETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator.
Output Inductor Selection
The value of the output inductor is chosen by balancing ripple current with transient response capability. A value of 1.7 mH will yield about 3.0 A peak-to-peak ripple current when converting from 5.0 V to 2.5 V at 250 kHz. It is important that the rated inductor current is not exceeded during full load, and that the saturation current is not less than the expected peak current. Low ESR inductors may be required to minimize DC losses and temperature rises.
Input Capacitor Selection
Power MOSFETs are chosen by balancing the cost with the requirements for the current load of the memory system and the efficiency of the converter provided. The selections criteria can be based on the drain-to-source voltage, drain-to-current, on-resistance RDS(on), and input gate capacitance. Low RDS(on) and high drain-to-current power MOSFETs are usually preferred to achieve the high current requirement of the DDR memory system and MCH, as well as the high efficiency of the converter. The tradeoff is a corresponding increase in the input gate capacitor of the power MOSFETs.
PCB Layout Consideration
Input capacitors for PWM power supplies are required to provide a stable, low impedance source node for the buck regulator to convert from. The usual practice is to use a combination of electrolytic capacitors and multi-layer ceramic capacitors to provide bulk capacitance and high frequency noise suppression. It is important that the capacitors are rated to handle the AC ripple current at the input of the buck regulators, as well as the input voltage. In the NCP5210 the DDQ and MCH regulators are interleaved (out of phase by 180) to reduce the peak AC input current.
Output Capacitor Selection
With careful PCB layout the NCP5210 can supply 20 A or more current. It is very important to use wide traces or large copper shades to carry current from the input node through the MOSFET switches, inductor, and to the output filters and load. Reducing the length of high current nodes will reduce losses and reduce parasitic inductance. It is usually best to locate the input capacitors, the MOSFET switches, and the output inductor in close proximity to reduce DC losses, parasitic inductance and radiated EMI. The sensitive voltage feedback and compensation networks should be placed near NCP5210 and away from the switch nodes and other noisy circuit elements. Placing compensation components near each other will minimize the loop area and further reduce noise susceptibility.
Optional Boost Voltage Configuration
Output capacitors are chosen by balancing the cost with the requirements for low output ripple voltage and transient voltage. Low ESR electrolytic capacitors can be effective at reducing ripple voltage at 250 kHz. Low ESR ceramic capacitors are most effective at reducing output voltage excursions caused by fast load steps of system memory and the memory controller.
12VATX TP2 D2 BAT54HT1 C27 100 nF NCP5210
SW_DDQ 20 BG_DDQ 19 TG_DDQ 18 BOOT 17 5VDUAL 16
The charge pump circuit in Figure 19 can be used instead of boost voltage scheme of Figure 18. The advantage in Figure 19 is the elimination of the requirement for the Zener clamp. The tradeoff is slightly less boost voltage and a corresponding increase in MOSFET conduction losses.
5VDUAL TP2 D1 BAT54HT1 D1
BAT54HT1 5VDUAL 4 R2 4.7 1 Q2 3 NTD40N03 R3 1k R4 4.7 4 DPAK Q2 NTD40N03 3
C4 5.6 nF L VDDQ C6 4.7 mF + C7 C25 + 2200 2200 mF mF
TP5 R15 2.5 VDDQ 1k
15 COMP_1P5 BUF_CUT 14
TG_1P5 13
1
GND_1P5
12 BG_1P5 11
Figure 19. Charge Pump Circuit at BOOT Pin
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NCP5210
Table 2. Bill of Material of NCP5210 Application Circuit
Ref Design Q1, Q2 Q3, Q4 D1, D2 U1 Description Power MOSFET N-Channel Power MOSFET N-Channel Rectifier Schottky Diode Controller Value 24 V, 4.8 mW, 85 A 25 V, 12.6 mW, 40 A 30 V 3-in-1 PWM Dual Buck and Linear Power Controller 13 V, 0.5 W 1.0 mH, 25 A 1.8 mH, 25 A 3300 mF, 6.3 V 470 mF, 35 V 100 mF, 50 V 470 mF, 16 V 470 mF, 10 V 2200 mF, 6.3 V 220 nF, 10 V 4.7 mF, 6.3 V 10 mF, 25 V 22 nF, 25 V 6.8 nF, 50 V 100 nF, 16 V 10 nF, 50 V 33 nF, 25 V 2.2 W 1.0 W 4.7 W 1.0 kW 20 kW 8.2 W 2.0 kW 2.2 kW 51 kW Qty 2 2 2 1 Part # NTD85N02R NTD40N03R BAT54HT1 NCP5210 Manufacturer ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor
Zener L1 L2, L3 C2, C3 C5 C21 C20 C13, C24 C7, C25, C15, C26 C11 C6, C12, C14 C22, C23 C4 C10, C17 C9, C18 C8, C16 C1 R2 R4 R9, R10 R3, R15, R16, R17 R7, R12 R6, R13 R8, R14 R5, R11 R18
Zener Diode Toroidal Choke Toroidal Choke Aluminum Electrolytic Capacitor Aluminum Electrolytic Capacitor Aluminum Electrolytic Capacitor Aluminum Electrolytic Capacitor Aluminum Electrolytic Capacitor Aluminum Electrolytic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor
1 1 2 2 1 1 1 2 4 1 3 2 1 2 2 2 1 1 1 2 4 2 2 2 2 1
MMSZ13T1 T60-26(6T) T50-26B(6T) EEUFJ0J332U EEUFC1V471 EEUFC1H101 EEUFC1C471 EEUFC1A471 EEUFC0J222SL ECJ1VB1A224K ECJHVB0J475M ECJ4YB1E106M ECJ1VB1E223K ECJ1VB1H682K ECJ1VB1C104K ECJ1VB1H103K ECJ1VB1E333K - - - - - - - - -
ON Semiconductor - - Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic - - - - - - - - -
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NCP5210
PACKAGE DIMENSIONS
QFN-20, DUAL-SIDED, 6x5 mm MN SUFFIX CASE 505AB-01 ISSUE A
D
A B
PIN 1 LOCATION
E
2X
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.65 0.75 0.20 REF 0.23 0.28 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.50 0.60
0.15 C
2X
0.15 C
TOP VIEW
0.10 C A2 0.08 C A1 SIDE VIEW (A3) A C
SEATING PLANE
DIM A A1 A2 A3 b D D2 E E2 e K L
D2
20X
L
e
1 10
20X
K
20 20X 11
E2
b 0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
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NCP5210
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NCP5210/D

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